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10/15 10/8 OS作業
名稱	10/8 OS作業
日期	10/15
課程名稱	作業系統
指導教師	劉艾華

1.
Because caches used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory. And the cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations.

Caches solve the transfer problem by providing a buffer of intermediate speed between the components. If the fast device finds the data it needs in the cache, it need not wait for the slower device.

The data in the cache must be kept consistent with the data in the components. If a component has a data value change, and the datum is also in the cache, the cache must also be updated. This is especially a problem on multiprocessor systems where more than one process may be accessing a datum.

Because faster storage tends to be more expensive.


2.
An interrupt is a signal from hardware (h/w interrupt) or software (s/w interrupt) to indicate the occurence of an event. It indicates the need of a change in execution. Interrupt handling or servicing of the interrupts depends upon the design of the operating system.

An interrupt can be used to signal the completion of an I/O to obviate the need for device polling. A trap can be used to call operating system routines or to catch arithmetic errors.

Yes.

User programs create traps for debugging purposes.


3.
A CPU uses complex algorithms and programming to interpret signals and code. And retrieves information from the code within programs. It reads it to understand what the code is for, and then it executes the instructions.
A device controller is a part of a computer system that makes sense of the signals going to, and coming from the CPU. Each device controller has a local buffer and a command register. It communicates with the CPU by interrupts.
The similarity between them is they catch the signals and save the signals in register,and then send the signals out.


4.
The process will stop working and save the handling condition,and OS will inquire about the interrupt vector base on the interrupt ID. And ISR（Interrupt Service Routine）will execution after get the beginning address of ISR. After ISR execution complete,it will return to the process before the interrupt.

更新日期：2015/10/15 上午 01:24:18